The present invention relates to a memory device and a method for fabricating the same, and more particularly, to a resistive memory device which uses resistance change, such as a resistive random access memory (ReRAM) device, and a method for fabricating the same.
Recently, researches on next-generation memory device, which can replace Dynamic Random Access Memory (DRAM) and flash memory, are actively being conducted.
One of such next-generation memory device is a resistive memory device that uses a resistive layer. The resistive layer includes a material of which resistance rapidly changes according to the applied bias and a switching is performed between two or more different resistive states.
The resistive layer material having the above described characteristic includes a binary oxide including a transition metal oxide or a perovskite-based material.
FIG. 1 illustrates a cross-sectional view of a first typical resistive memory device.
Referring to FIG. 1, the first typical resistive memory device includes a substrate 10. An insulation layer 11 including a contact plug 12 is formed over the substrate 10. A stack structure is formed over the insulation layer 11 and the contact plug 12.
The stack structure includes a bottom electrode 13 formed over the insulation layer 11 and in contact with the contact plug 12, a resistive layer 14, and an upper electrode 15. The stack structure including the bottom electrode 13, the resistive layer 14, and the upper electrode 15 is referred to as a resistive unit 100.
In the first typical resistive memory device, the resistive layer 14 is switched between high resistance state and low resistance state according to a bias applied to the bottom electrode 13 and the upper electrode 15. Thus, data corresponding to each resistance state are stored.
The above mentioned switching mechanism is briefly explained as follows. According to the applied bias, filamentary current paths are formed in the resistive layer 14 to have the low resistance state or the existing filamentary current paths are destroyed to allow the resistive layer to have the high resistance state.
There is, however, a limitation in providing a sufficient switching characteristic to the first typical resistive memory device. Generally, the dimensions of the bottom electrode 13 are substantially the same as or larger than that of the resistive layer 14. Thus, the size of the contacting area between the bottom electrode 13 and the resistive layer 14 depends on the dimensions of the resistive layer 14.
Consequently, the whole resistive layer 14 becomes a switching region when a certain bias is applied to the bottom electrode 13 and the upper electrode 15. When the whole resistive layer 14 becomes a switching region, it becomes difficult to uniformly control generation of filamentary current paths, and in particular, a high reset current may be necessitated. Thus, it becomes difficult to clearly distinguish between the two resistance states. Therefore, it is not easy to implement such a resistive memory device in a current application.
An article by Baek, I. G., Kim, D. C., Lee, M. J., Kim, H. J., Kim, E. K., Lee, M. S., Lee, J. E., Ahn, S. E., Seo, S., and Lee, J. H, entitled “Multi-layer Cross-point Binary Oxide Resistive Memory (OxRRAM) for Post-NAND Storage Application,” Institute of Electrical and Electronics Engineers (IEEE), Vol.-No.-[2005], p 769-772 (2005), discloses technology for improving the switching characteristic by forming a bottom electrode in a plug shape to reduce a contacting area between the bottom electrode and a resistive layer. This technology is described in detail hereinafter with reference to FIG. 2.
FIG. 2 illustrates a cross-sectional view of a second typical resistive memory device.
Referring to FIG. 2, the second typical resistive memory device includes a substrate 20. An insulation layer 21 including a contact plug 22 is formed over the substrate 20. A stack structure is formed over the insulation layer 21 and the contact plug 22.
The stack structure includes a resistive layer 23 formed over the insulation layer 21 and in contact with the contact plug 22 and an upper electrode 24. A resistive unit 200 includes the contact plug 22, the resistive layer 23, and the upper electrode 24.
In other words, unlike the first typical resistive memory device shown in FIG. 1 where a bottom electrode is formed separately from a contact plug, the contact plug 22 is used as a bottom electrode in the second typical resistive memory device shown in FIG. 2.
In FIG. 1, the entire resistive layer becomes a switching region. On the other hand, in FIG. 2, only a portion of the resistive layer 23 in contact with the contact plug 22 becomes a switching region (refer to reference denotation ‘A’ shown in FIG. 2).
Therefore, it becomes easier to uniformly control the generation of filamentary current paths in the second typical resistive memory device shown in FIG. 2. In particular, the number of filamentary current paths decreases as the switching region A decreases so that a reset current may be reduced.
Consequently, the switching characteristic of the device improves. Furthermore, as the dimensions of the contact plug 22 are decreased, the number and distribution of the filamentary current paths may be decreased as well, further enhancing the switching characteristic of the device.
As semiconductor devices are becoming highly integrated recently, the size of devices is getting smaller. It may be generally demanded that the dimensions of a contact plug be further reduced in fabricating a resistive memory device which employs a contact plug as a bottom electrode. However, reducing the dimensions of a contact plug further is reaching a maximum limit due to the process limitations associated with photolithography process and etching process. Therefore, an improved resistive memory device and a method for fabricating the same are in need to overcome the limitations.